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256k x18 pipelined sram with nobl? architecture cy7c1352 cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 march 14, 2001 1cy7c1352 features ? pin compatible and functionally equivalent to zbt? devices mcm63z818 and mt55l256l18p supports 143-mhz bus operations with zero wait states ? data is transferred on every clock internally self-timed output buffer control to eliminate the need to use oe fully registered (inputs and outputs) for pipelined operation byte write capability 256k x 18 common i/o architecture single 3.3v power supply fast clock-to-output times ? 4.0 ns (for 143-mhz device) ? 4.2 ns (for 133-mhz device) ? 5.0 ns (for 100-mhz device) ? 7.0 ns (for 80-mhz device) clock enable (cen ) pin to suspend operation synchronous self-timed writes asynchronous output enable jedec-standard 100-pin tqfp package burst capability?linear or interleaved burst order low standby power functional description the cy7c1352 is a 3.3v 256k by 18 synchronous-pipelined burst sram designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. the cy7c1352 is equipped with the advanced no bus latency? (nobl?) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. this feature dramatically improves the throughput of the sram, especially in systems that require frequent read/write transitions.the cy7c1352 is pin/functionally com- patible to zbt? srams mcm63z819 and mt55l256l18p. all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the rising edge of the clock. the clock input is qualified by the clock enable (cen ) signal, which when deasserted suspends operation and extends the previ- ous clock cycle. maximum access delay from the clock rise is 4.0 ns (143-mhz device). write operations are controlled by the four byte write select (bws [1:0] ) and a write enable (we ) input. all writes are con- ducted with on-chip synchronous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank se- lection and output three-state control. in order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. . nobl and no bus latency are trademarks of cypress semiconductor corporation. zbt is a trademark of integrated device technology. clk a [17:0] cen we bws ce 1 ce ce 2 oe output 256kx18 memory array clk logic block diagram dq [15:0] data-in reg. q d ce control and write logic 3 [1:0] registers and logic adv/ld 18 18 18 18 18 18 dp [1:0] mode selection guide 7c1352-143 7c1352-133 7c1352-100 7c1352-80 maximum access time (ns) 4.0 4.2 5.0 7.0 maximum operating current (ma) commercial 450 400 350 300 maximum cmos standby current (ma) commercial 5 5 5 5
cy7c1352 2 pin configuration 100-pin tqfp a 5 a 4 a 3 a 2 a 1 a 0 dnu dnu v ss v dd dnu a 10 a 11 a 12 a 13 a 14 a 16 a 17 nc nc v ddq v ss nc dp 0 dq 7 dq 6 v ss v ddq dq 5 dq 4 v ss v dd v dd dq 3 dq 2 v ddq v ss dq 1 dq 0 nc nc v ss v ddq nc nc nc nc nc nc v ddq v ss nc nc dq 8 dq 9 v ss v ddq dq 10 dq 11 v ddq v dd v dd v ss dq 12 dq 13 v ddq v ss dq 14 dq 15 dp 1 nc v ss v ddq nc nc nc a6 a7 ce 1 ce 2 nc nc bws 1 bws 0 ce 3 v dd v ss clk we cen oe nc a 8 a 9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a 15 nc adv/ld v ss mode dnu cy7c1352
cy7c1352 3
cy7c1352 4 pin definitions pin number name i/o description 80, 50 ? 44, 81 ? 82, 99 ? 100, 32 ? 37 a [17:0] input- synchronous address inputs used to select one of the 262,144 address locations. sampled at the rising edge of the clk. 94, 93 bws [1:0] input- synchronous byte write select inputs, active low. qualified with we to conduct writes to the sram. sampled on the rising edge of clk. bws 0 controls dq [7:0] and dp 0 , bws 1 controls dq [15:8] and dp 1 . see write cycle description table for details. 88 we input- synchronous write enable input, active low. sampled on the rising edge of clk if cen is active low. this signal must be asserted low to initiate a write sequence. 85 adv/ld input- synchronous advance/load input used to advance the on-chip address counter or load a new address. when high (and cen is asserted low) the internal burst counter is advanced. when low, a new address can be loaded into the device for an ac- cess. after being deselected, adv/ld should be driven low in order to load a new address. 89 clk input-clock clock input. used to capture all synchronous inputs to the device. clk is qualified with cen . clk is only recognized if cen is active low. 98 ce 1 input- synchronous chip enable 1 input active low. sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. 97 ce 2 input- synchronous chip enable 2 input active high. sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. 92 ce 3 input- synchronous chip enable 3 input, active low. sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. 86 oe input- asynchronous output enable, active low. combined with the synchronous logic block inside the device to control the direction of the i/o pins. when low, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. oe is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. 87 cen input- synchronous clock enable input, active low. when asserted low the clock signal is recog- nized by the sram. when deasserted high the clock signal is masked. since deasserting cen does not deselect the device, cen can be used to extend the previous cycle when required. 23 ? 22, 19 ? 18, 13 ? 12, 9 ? 8, 73 ? 72, 69 ? 68, 63 ? 62, 59 ? 58 dq [15:0] i/o- synchronous bidirectional data i/o lines. as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by a [16:0] during the previous clock rise of the read cycle. the direction of the pins is controlled by oe and the internal control logic. when oe is asserted low, the pins can behave as outputs. when high, dq [15:0] are placed in a three-state condition. the outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of oe . 24, 74 dp [1:0] i/o- synchronous bidirectional data parity i/o lines. functionally, these signals are identical to dq [15:0] . during write sequences, dp 0 is controlled by bws 0 and dp 1 is con- trolled by bws 1 31 mode input strap pin mode input. selects the burst order of the device. tied high selects the inter- leaved burst order. pulled low selects the linear burst order. mode should not change states during operation. when left floating, mode will default high to an interleaved burst order. 15, 16, 41, 65, 66, 91 v dd power supply power supply inputs to the core of the device. should be connected to 3.3v power supply. 4, 11, 14, 20, 27, 54, 61, 70, 77 v ddq i/o power supply power supply for the i/o circuitry. should be connected to a 3.3v power supply. 5, 10, 17, 21, 26, 40, 55, 60, 64, 67, 71, 76, 90 v ss ground ground for the device. should be connected to ground of the system.
cy7c1352 5 introduction functional overview the cy7c1352 is a synchronous-pipelined burst sram de- signed specifically to eliminate wait states during write-read transitions. all synchronous inputs pass through input regis- ters controlled by the rising edge of the clock. the clock signal is qualified with the clock enable input signal (cen ). if cen is high, the clock signal is not recognized and all internal states are maintained. all synchronous operations are qualified with cen . all data outputs pass through output registers controlled by the rising edge of the clock. maximum access delay from the clock rise (t co ) is 4.0 ns (143-mhz device). accesses can be initiated by asserting all three chip enables (ce 1 , ce 2 , ce 3 ) active at the rising edge of the clock. if clock enable (cen ) is active low and adv/ld is asserted low, the address presented to the device will be latched. the access can either be a read or write operation, depending on the sta- tus of the write enable (we ). bws [1:0] can be used to conduct byte write operations. write operations are qualified by the write enable (we ). all writes are simplified with on-chip synchronous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) simplify depth expansion. all operations (reads, writes, and deselects) are pipelined. adv/ld should be driven low once the device has been de- selected in order to load a new address for the next operation. single read accesses a read access is initiated when the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, (3) the write enable input signal we is deasserted high, and (4) adv/ld is asserted low. the address presented to the address inputs (a 0 ? a 17 ) is latched into the address register and presented to the memory core and control logic. the control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. at the rising edge of the next clock the requested data is allowed to propa- gate through the output register and onto the data bus within 4.0 ns (143-mhz device) provided oe is active low. after the first clock of the read access the output buffers are controlled by oe and the internal control logic. oe must be driven low in order for the device to drive out the requested data. during the second clock, a subsequent operation (read/write/dese- lect) can be initiated. deselecting the device is also pipelined. therefore, when the sram is deselected at clock rise by one of the chip enable signals, its output will three-state following the next clock rise. burst read accesses the cy7c1352 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. adv/ld must be driven low in order to load a new address into the sram, as described in the single read access section above. the sequence of the burst counter is determined by the mode input signal. a low input on mode selects a linear burst mode, a high selects an interleaved burst sequence. both burst counters use a0 and a1 in the burst sequence, and will wrap-around when incremented sufficiently. a high input on adv/ld will increment the internal burst counter regardless of the state of chip enables inputs or we . we is latched at the beginning of a burst cycle. therefore, the type of access (read or write) is maintained throughout the burst sequence. single write accesses write accesses are initiated when the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, and (3) the write signal we is asserted low. the address presented to a 0 ? a 17 is loaded into the address register. the write signals are latched into the control logic block. on the subsequent clock rise the data lines are automatically three-stated regardless of the state of the oe input signal. this allows the external logic to present the data on dq [15:0] and dp [1:0] . in addition, the address for the subsequent access (read/write/deselect) is latched into the address register (provided the appropriate control signals are asserted). on the next clock rise the data presented to dq [15:0] and dp [1:0] (or a subset for byte write operations, see write cycle description table for details) inputs is latched into the device and the write is complete. the data written during the write operation is controlled by bws [1:0] signals. the cy7c1352 provides byte write capabil- ity that is described in the write cycle description table. assert- ing the write enable input (we ) with the selected byte write select (bws [1:0] ) input will selectively write to only the desired bytes. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. byte write capability has been included in order to greatly simplify read/modify/write sequences, which can be reduced to sim- ple byte write operations. because the cy7c1352 is a common i/o device, data should not be driven into the device while the outputs are active. the output enable (oe ) can be deasserted high before present- ing data to the dq [15:0] and dp [1:0] inputs. doing so will three-state the output drivers. as a safety precaution, dq [15:0] 1 ? 3, 6 ? 7, 25, 28 ? 30, 51 ? 53, 56 ? 57, 75, 78 ? 79, 95 ? 96 nc - no connects. these pins are not connected to the internal device. 83, 84 nc - no connects. reserved for address inputs for depth expansion. pin 83 is re- served for 512k depth and pin 84 is reserved for 1-mb depth devices. 38, 39, 42, 43 dnu - do not use pins. these pins should be left floating or tied to v ss . pin definitions (continued) pin number name i/o description
cy7c1352 6 and dp [1:0] are automatically three-stated during the data por- tion of a write cycle, regardless of the state of oe . burst write accesses the cy7c1352 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four write operations without reasserting the address inputs. adv/ld must be driven low in order to load the initial ad- dress, as described in the single write access section above. when adv/ld is driven high on the subsequent clock rise, the chip enables (ce 1 , ce 2 , and ce 3 ) and we inputs are ig- nored and the burst counter is incremented. the correct bws [1:0] inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. cycle description truth table [ 1, 2, 3, 4, 5, 6 ] operation address used ce cen adv/ ld/ we bws x clk comments deselected external 1 0 l x x l-h i/os three-state following next rec- ognized clock. suspend - x 1 x x x l-h clock ignored, all operations suspended. begin read external 0 0 0 1 x l-h address latched. begin write external 0 0 0 0 valid l-h address latched, data presented two valid clocks later. burst read operation internal x 0 1 x x l-h burst read operation. previous access was a read operation. ad- dresses incremented internally in conjunction with the state of mode. burst write operation internal x 0 1 x valid l-h burst write operation. previous access was a write operation. ad- dresses incremented internally in conjunction with the state of mode. bytes written are deter- mined by bws [1:0] . interleaved burst sequence first address second address third address fourth address ax+1, ax ax+1, ax ax+1, ax ax+1, ax 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst sequence first address second address third address fourth address ax+1, ax ax+1, ax ax+1, ax ax+1, ax 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 write cycle descriptions [1, 2] function we bws 1 bws 0 read 1xx write ? no bytes written 0 1 1 write byte 0 ? (dq [7:0] and dp 0 )010 write byte 1 ? (dq [15:8] and dp 1 )001 write all bytes 0 0 0 notes: 1. x=?don't care?, 1=logic high, 0=logic low, ce stands for all chip enables active. bws x = 0 signifies at least one byte write select is active, bws x = valid signifies that the desired byte write selects are asserted, see write cycle description table for details. 2. write is defined by we and bws [1:0] . see write cycle description table for details. 3. the dq and dp pins are controlled by the current cycle and the oe signal. 4. cen =1 inserts wait states. 5. device will power-up deselected and the i/os in a three-state condition, regardless of oe . 6. oe assumed low.
cy7c1352 7 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ..................................... ? 65 c to +150 c ambient temperature with power applied .................................................. ? 55 c to +125 c supply voltage on v dd relative to gnd .........? 0.5v to +4.6v dc voltage applied to outputs in high z state [9] .....................................? 0.5v to v ddq + 0.5v dc input voltage [9] ..................................? 0.5v to v ddq + 0.5v current into outputs (low) .........................................20 ma static discharge voltage .......................................... >2001v (per mil-std-883, method 3015) latch-up current.................................................... >200 ma operating range range ambient temperature [7] v dd /v ddq com?l 0 c to +70 c 3.3v 5% ind?l ?40c to +85c 3.3v 5% electrical characteristics over the operating range parameter description test conditions min. max. unit v dd power supply voltage 3.135 3.465 v v ddq i/o supply voltage 3.135 3.465 v v oh output high voltage v dd = min., i oh = ?4.0 ma [8] 2.4 v v ol output low voltage v dd = min., i ol = 8.0 ma [8] 0.4 v v ih input high voltage 2.0 v dd + 0.3v v v il input low voltage [9] ? 0.3 0.8 v i x input load current gnd v i v ddq ? 5 5 a input current of mode ? 30 30 a i oz output leakage current gnd v i v ddq, output disabled ? 5 5 a i cc v dd operating supply v dd = max., i out = 0 ma, f = f max = 1/t cyc 7.0-ns cycle, 143 mhz 450 ma 7.5-ns cycle, 133 mhz 400 ma 10-ns cycle, 100 mhz 350 ma 12.5-ns cycle, 80 mhz 300 ma i sb1 automatic ce power-down current?ttl inputs max. v dd , device deselected, v in v ih or v in v il f = f max = 1/t cyc 7.0-ns cycle, 143 mhz 70 ma 7.5-ns cycle, 133 mhz 60 ma 10-ns cycle, 100 mhz 50 ma 12.5-ns cycle, 80 mhz 40 ma i sb2 automatic ce power-down current?cmos inputs max. v dd , device deselected, v in 0.3v or v in > v ddq ? 0.3v, f = 0 all speed grades 5 ma i sb3 automatic ce power-down current?cmos inputs max. v dd , device deselected, or v in 0.3v or v in > v ddq ? 0.3v f = f max = 1/t cyc 7.0-ns cycle, 143 mhz 60 ma 7.5-ns cycle, 133 mhz 50 ma 10-ns cycle, 100 mhz 40 ma 12.5-ns cycle, 80 mhz 30 ma notes: 7. t a is the case temperature. 8. the load used for v oh and v cl testing is shown in part (b) of a/c test loads and waveforms. 9. minimum voltage equals ?2.0v for pulse duration less than 20 ns.
cy7c1352 8 capacitance [10] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3v. v ddq = 3.3v 4 pf c clk clock input capacitance 4 pf c i/o input/output capacitance 4 pf ac test loads and waveforms thermal resistance description test conditions symbol tqfp typ. units notes thermal resistance (junction to ambient) still air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board ja 28 c/w 10 thermal resistance (junction to case) jc 4c/w10 note: 10. tested initially and after any design or process change that may affect these parameters. 11. a/c test conditions assume signal transition time of 2 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3.0v, and output loading shown in (a) of ac test loads and waveforms. 3.0v gnd output r=317 ? r=351 ? 5pf including jig and scope (a) (b) all input pulses 1352-2 output r l =50 ? z 0 =50 ? v l = 1.5v 3.3v [11]
cy7c1352 9 switching characteristics over the operating range [11,12,13] -143 -133 -100 -80 parameter description min. max. min. max. min. max. min. max. unit t cyc clock cycle time 7.0 7.5 10 12.5 ns t ch clock high 2.0 2.5 3.5 4.0 ns t cl clock low 2.0 2.5 3.5 4.0 ns t as address set-up before clk rise 2.0 2.0 2.2 2.5 ns t ah address hold after clk rise 0.5 0.5 0.5 1.0 ns t co data output valid after clk rise 4.0 4.2 5.0 7.0 ns t doh data output hold after clk rise 1.5 1.5 1.5 1.5 ns t cens cen set-up before clk rise 2.0 2.0 2.2 2.5 ns t cenh cen hold after clk rise 0.5 0.5 0.5 1.0 ns t wes gw , bws [1:0] set-up before clk rise 2.0 2.0 2.2 2.5 ns t weh gw , bws [1:0] hold after clk rise 0.5 0.5 0.5 1.0 ns t als adv/ld set-up before clk rise 2.0 2.0 2.2 2.5 ns t alh adv/ld hold after clk rise 0.5 0.5 0.5 1.0 ns t ds data input set-up before clk rise 1.7 1.7 2.0 2.5 ns t dh data input hold after clk rise 0.5 0.5 0.5 1.0 ns t ces chip enable set-up before clk rise 2.0 2.0 2.2 2.5 ns t ceh chip enable hold after clk rise 0.5 0.5 0.5 1.0 ns t chz clock to high-z [10, 12, 13, 14] 1.5 3.5 1.5 3.5 1.5 3.5 1.5 5.0 ns t clz clock to low-z [10, 12, 13, 14] 1.5 1.5 1.5 1.5 ns t eohz oe high to output high-z [10, 12, 13, 14] 4.0 4.2 5.0 7.0 ns t eolz oe low to output low-z [10, 12, 13, 14] 0 0 0 0 ns t eov oe low to output valid [12] 4.0 4.2 5.0 7.0 ns note: 12. t chz , t clz , t oev , t eolz , and t eohz are specified with a/c test conditions shown in part (a) of ac test loads and waveforms. transition is measured 200 mv from steady-state voltage. 13. at any given voltage and temperature, t eohz is less than t eolz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. device is designed to achieve high-z prior to low-z under the same system conditions. 14. this parameter is sampled and not 100% tested.
cy7c1352 10 switching waveforms cen clk address ce we & 1a data- in/out t cyc t ch t cl ra1 t ah t as t ws t wh t ces t ceh t co q4 = don?t care = undefined the combination of we & bws [1:0] defines a write cycle (see write cycle description table). d5 in out read write deselect write read read read suspend read deselect deselect wa2 ra3 ra4 wa5 ra6 ra7 t clz t doh 1a t chz ce is the combination of ce 1 , ce 2 , and ce 3 . all chip enables need to be active in order to select the device. any chip enable can deselect the device. rax stands for read address x, wax stands for device originally deselected write address x, dx stands for data-in for location x, qx stands for data-out for location x. adv/ld held low. q7 out t chz t cens t cenh t doh bws [1:0] read/write/deselect sequence cen high blocks q6 out all synchronous inputs t ds t dh oe held low. q1 out q3 out d2 in
cy7c1352 11 switching waveforms (continued) adv/ld clk address ce 1a data- in/out t cyc t ch t cl t als t alh ra1 t ah t as t ces t ceh t co q1 = don?t care = undefined the combination of we & bws [1:0] defines a write cycle (see write cycle description table). out begin read burst read t clz t doh ce is the combination of ce 1 , ce 2 , and ce 3 . all chip enables need to be active in order to select the device. any chip enable can deselect the device. rax stands for read address x, wa stands for device originally deselected write address x, dx stands for data-in for location x, qx stands for data-out for location x. cen held wa2 q1+1 out q1+2 out q1+3 out ra3 t clz t chz d2+1 in d2+2 in d2+3 in d2 in t co q3 out t ds t dh burst read burst read begin write burst write burst write burst write begin read burst read burst read burst sequences bws [1:0] t ws t wh we t ws t wh low. during burst writes, byte writes can be conducted by asserting the appropriate bws [1:0] input signals. burst order determined by the state of the mode input. cen held low. oe held low.
cy7c1352 12 document #: 38 ? 00934-*b switching waveforms (continued) oe three-state i/o?s oe timing t eohz t eov t eolz ordering information speed (mhz) ordering code package name package type operating range 143 cy7c1352-143ac a101 100-lead (14 x 20 x 1.4 mm) thin quad flat pack commercial 133 cy7c1352-133ac a101 100-lead (14 x 20 x 1.4 mm) thin quad flat pack commercial 133 CY7C1352-133AI a101 100-lead (14 x 20 x 1.4 mm) thin quad flat pack industrial 100 cy7c1352-100ac a101 100-lead (14 x 20 x 1.4 mm) thin quad flat pack commercial 100 cy7c1352-100ai a101 100-lead (14 x 20 x 1.4 mm) thin quad flat pack industrial
cy7c1352 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagram 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 51-85050-a

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